The present invention relates generally to calibrating electron beam defect inspection tools used for semiconductor testing.
Semiconductor wafers, including central processing units (CPUs), can be tested during manufacturing to ensure quality control. One way wafers can be tested is using an electron beam (e-beam) inspection tool, which detects, by way of irradiating a wafer with an electron beam, surface defects as well as so-called xe2x80x9cvoltage contrast defectsxe2x80x9d that can be caused by defects in layers underlying the surface layer. Such voltage contrast occurs as a result of differential charge build-up on features, such as metal landing pads. When negative charges accumulate on a feature, the resulting negative potential repels electrons, causing the feature to appear bright under an electron microscope. In contrast, a positive charge build-up causes the feature to appear dark. In this way, an e-beam tool can be used to derive, from the contrast of the return image, whether a defect such as a short or open exists in the wafer.
As recognized by the present invention, it would be advantageous to determine whether and how accurately an e-beam defect inspection tool senses voltage contrast defects, so that the tool can be calibrated and/or characterized. For instance, it would be advantageous to determine whether an e-beam tool senses all defects, or only defects of a certain size. Moreover, the present invention recognizes that it would be advantageous to determine how accurately an e-beam defect inspection tool indicates varying degrees of defects by ascertaining whether the gray scale output by the tool in the presence of voltage contrast defects is correct. Still further, the present invention recognizes that it would be advantageous to make such calibration/characterization measurements in a robust manner, e.g., including during scans of actual product dies, random logic scans, and array mode scans. Having made the above critical observations, the present invention provides the below-solutions to one or more of the observations.
A system includes a semiconductor product that in turn includes repeating electronic test features, at least one of which is formed with a deliberate voltage contrast defect. An electron beam defect inspection tool is disposed adjacent the semiconductor product to detect the defect therein and output a signal in response thereto.
In another aspect, a method for calibrating an electron beam (e-beam) inspection tool includes deliberately forming a voltage contrast defect in a first test feature on a semiconductor device that includes plural repeating test features. The method also includes scanning the device using the e-beam defect inspection tool to render a scan signal. Then, using the scan signal, the inspection tool is calibrated and/or characterized.
In a preferred embodiment, the act of forming the defect includes deliberately establishing an electrical connectivity of the first test feature to be different than analogous electrical connectivities of the repeating test features other than the first test feature. Specifically, the act of forming the defect includes deliberately introducing an electrical short in the first test feature, or deliberately introducing an electrical open in the first test feature, or deliberately introducing an abnormal electrical resistance in the first test feature.
In one non-limiting example, to form a short, first contacts are formed in a first level in electrical contact with a substrate, and second contacts are formed in a second level above the first level. One second contact can be in electrical contact with a first contact such that the second contact is shorted to the substrate.
Or, to establish high resistances or opens, plural identical electronic features can be formed above a semiconductor substrate, with each feature having at least one contact electrically connecting the feature to the substrate. With this structure, an open feature or abnormal resistivity feature is deliberately established by establishing a lesser (or zero) number of contacts for the open feature compared to the number of contacts established for features other than the open feature.
A semiconductor product includes a wafer with plural product dies. Plural test features are in scribe lines of the wafer for in-place testing.
In another aspect, a method of using a wafer including plural product dies and plural test features in scribe lines of the wafer includes scanning the product dies and test features using an e-beam inspection tool, and then comparing scan signals of voltage contrast defects in product dies with scan signals of voltage contrast defects in test features.
Other features of the present invention are disclosed or apparent in the section entitled xe2x80x9cDETAILED DESCRIPTION OF THE INVENTIONxe2x80x9d.